Cadence Joules RTL Power Solution is an RTL and gate-level power analysis tool for SoC design teams to estimate, debug, and reduce power during RTL / pre-implementation stages. It is designed to maintain correlation with downstream implementation and signoff power analysis. The tool provides time-based (frame-based) power reporting driven by realistic stimulus (simulation/emulation), along with facilities for "what-if" exploration and RTL power reduction guidance.
Core claims and capabilities described by Cadence include:
- Time-based RTL power analysis with system-level runtimes and capacity; Cadence claims substantial runtime improvements compared with other methods.
- Correlation target: Cadence claims RTL power estimates that are close to signoff, within a modest margin, including glitch power derived from RTL stimulus.
- A single power engine across the flow (RTL → synthesis → P&R → gate-level) intended to reduce correlation issues.
- Integrations with Cadence platforms (Xcelium, Palladium, Genus, Innovus, Stratus) to connect verification workloads and implementation optimization.
- An "Ideal Power" methodology (theoretical minimum power vs observed) to identify activity that may be reduced and to guide RTL changes.
Sources: Official vendor product overview and product datasheet.