Synopsys ParagonX is an integrated circuit (IC) layout parasitics analysis, visualization, and debugging tool intended to help analog/custom/mixed-signal teams determine which extracted parasitics (resistance, capacitance, coupling, etc.) are contributing to performance or robustness issues and to identify the physical root cause in layout earlier than workflows that rely solely on post-layout simulation.
The vendor describes it as a visual tool that operates after extraction and that can be used prior to completing layout verification such as LVS.
Key functional areas emphasized by the vendor include:
- Analysis of parasitic resistance, capacitance, and crosstalk on large designs (vendor materials reference reductions in runtime for large netlists)
- Visual root-cause debugging in a graphical user interface
- Sensitivity-driven identification of high-impact parasitics
- Automated net/device matching and electrical rule check (ERC)-style checks
- Scripting and extensibility via Python
- Integration with Synopsys StarRC and other EDA workflows (vendor-stated integration)
Sources cited by the vendor include product pages and webinar materials published by Synopsys and related press coverage.