Synopsys Platform Architect is a SystemC / Transaction-Level Modeling (TLM)–based environment used for early SoC (and multi-die/chiplet) architecture exploration, focusing on performance and power tradeoffs prior to RTL completion. The tool is intended for early-stage architectural analysis to predict architectural KPIs and reduce late-stage design changes by enabling architects to simulate memory/interconnect behavior, hardware/software partitioning, and workload-driven behavior using pre-RTL models.
Synopsys describes Platform Architect as:
- SystemC standards-based (IEEE 1666) and transaction-level simulation driven for early analysis and optimization.
- Focused on interconnect/memory subsystem performance, power analysis, design space exploration, and workload capture (task/trace-based).
Key functional themes referenced in product materials:
- Architecture exploration and design space exploration (sweeping configurations; sensitivity analysis).
- Performance analysis and root-cause analysis for latency/bandwidth/utilization bottlenecks.
- Power modeling and monitoring at system level, including UPF power monitors (vendor statements).
- Model library and ecosystem integration (Arm, Arteris, memory controllers, traffic generators, die-to-die/UCIe, etc.).
(Official vendor product overview and model library pages.)