Synopsys Static & Formal Verification
Synopsys Static & Formal Verification is a portfolio of EDA verification tools that detects RTL and SoC integration issues early using static analysis (lint, CDC/RDC, structural/semantic checks) and formal methods (property proving, equivalence-style checks, connectivity and X-propagation analysis), and integrates with Synopsys verification flows for signoff on large designs.
Est 1986|Raised $2.1B